VERIFICATION AND VALIDATION ISSUES IN MANUFACTURING MODELS

被引：9

作者：

JAGDEV, HS ^{[1
]}

BROWNE, J ^{[1
]}

JORDAN, P ^{[1
]}

机构：

[1] NATL UNIV IRELAND UNIV COLL GALWAY,CIMRU,GALWAY,IRELAND

来源：

COMPUTERS IN INDUSTRY | 1995年 / 25卷 / 03期

关键词：

VERIFICATION; VALIDATION; MANUFACTURING MODELS;

D O I：

10.1016/0166-3615(94)00045-R

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

Verification and validation are two techniques employed during the development of computer programs and the modelling of systems. Each of these techniques has a unique scope. Both techniques are an inherent part of the problem specification, program coding and the final implementation of the computer software in a real-life environment. The issues of verification and validation have become all the more critical as the scope of modern-day computer programs have evolved from data manipulation to performing cognitive tasks. This paper discusses the verification and validation issues in all three phases of software development. It introduces the basic definitions of models, verification and validation and goes on to describe their scope. Finally, the paper describes the lessons learnt from the validation of a Generalised Real-Time Job Shop Control System in a real-life manufacturing environment.

引用

页码：331 / 353

页数：23