CHIP ARCHITECTURES FOR PARALLEL PROCESSING

被引:0
|
作者
DETTMER, R
机构
来源
ELECTRONICS AND POWER | 1985年 / 31卷 / 03期
关键词
D O I
10.1049/ep.1985.0152
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:227 / 231
页数:5
相关论文
共 50 条
  • [31] Architectures for parallel query processing on networks of workstations
    Dandamudi, SP
    Jain, G
    INTERNATIONAL SOCIETY FOR COMPUTERS AND THEIR APPLICATIONS 10TH INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED COMPUTING SYSTEMS, 1997, : 444 - 451
  • [32] Programmable parallel coprocessor architectures for reconfigurable system-on-chip
    Williams, J
    Bergmann, N
    2004 IEEE INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, PROCEEDINGS, 2004, : 193 - 200
  • [33] Correction to: Parallel and distributed Processing: advances on architectures and applications of parallel systems
    Diego R. Llanos
    Dora B. Heras
    Computing, 2023, 105 : 913 - 913
  • [34] Parallel algorithms and processing architectures for space-time adaptive processing
    Farina, A
    Timmoneri, L
    ICR '96 - 1996 CIE INTERNATIONAL CONFERENCE OF RADAR, PROCEEDINGS, 1996, : 770 - 774
  • [35] A parallel processing chip with embedded DRAM macros
    Sunaga, T
    Miyatake, H
    Kitamura, K
    Kogge, PM
    Retter, E
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (10) : 1556 - 1559
  • [36] Topological limits to the parallel processing capability of network architectures
    Petri, Giovanni
    Musslick, Sebastian
    Dey, Biswadip
    ozcimder, Kayhan
    Turner, David
    Ahmed, Nesreen K.
    Willke, Theodeore L.
    Cohen, Jonathan D.
    NATURE PHYSICS, 2021, 17 (05) : 646 - +
  • [37] MAPPING SIGNAL-PROCESSING ALGORITHMS ON PARALLEL ARCHITECTURES
    SAMMUR, NM
    HAGAN, MT
    JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 1990, 8 (02) : 180 - 185
  • [38] PARALLEL PROCESSING - FUNCTION-DIRECTED AND NEURAL ARCHITECTURES
    BRAUSE, R
    MICROPROCESSING AND MICROPROGRAMMING, 1988, 24 (1-5): : 597 - 597
  • [39] Parallel Pipeline on Heterogeneous Multi-Processing Architectures
    Rodriguez, Andres
    Navarro, Angeles
    Asenjo, Rafael
    Vilches, Antonio
    Corbera, Francisco
    Garzaran, Maria
    2015 IEEE TRUSTCOM/BIGDATASE/ISPA, VOL 3, 2015, : 166 - 171
  • [40] A novel division algorithm and architectures for parallel and sequential processing
    Tatas, K
    Soudris, DJ
    Siomos, D
    Thanailakis, A
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2005, 14 (02) : 281 - 295