BOUNCE: A New High-Resolution Time-Interval Measurement Architecture

被引:15
作者
Salomon, Ralf [1 ]
Joost, Ralf [1 ]
机构
[1] Univ Rostock, Inst Appl Micro Elect & Comp Sci, D-18051 Rostock, Germany
关键词
Delay effects; delay estimations; field programmable gate arrays;
D O I
10.1109/LES.2009.2034711
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Measuring the duration of a time interval is a discretization process in which an input signal is sampled at discrete time steps. Most digital systems generate these time steps by active components, such as a generator, flip-flops, dedicated delay elements, gates, inverters, and the like, whose signal propagation time determine the system's resolution. This paper presents a new time-interval measurement architecture, called BOUNCE, in which the delays are realized by the simplest elements possible: the (metal) wires between the logic elements within the chip. Standard RS latches serve as the sampling units. Even though the requirements with respect to setup and hold times of these latches are not met, the architecture operates quite reliably: on an Altera Stratix II field-programmable gate array, BOUNCE yields a time resolution better than 4 ps. Due to its architecture, BOUNCE is ideally suited to be implemented on field-programmable gate arrays and can thus be realized as an embedded system on its own or as part of an existing one.
引用
收藏
页码:56 / 59
页数:4
相关论文
共 9 条
[1]   Design of sub-10-picoseconds on-chip time measurement circuit [J].
Abas, MA ;
Russell, G ;
Kinniment, DJ .
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, :804-809
[2]  
Cicalese R., 2008, P 10 C ASTR PART SPA
[3]   A delay line based CMOS time digitizer IC with 13 ps single-shot precision [J].
Jansson, J ;
Mäntyniemi, A ;
Kostamovaara, J .
2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, :4269-4272
[4]   Review of methods for time interval measurements with picosecond resolution [J].
Kalisz, J .
METROLOGIA, 2004, 41 (01) :17-32
[5]  
Maxfield C, 2004, DESIGN WARRIORS GUID
[6]  
Muntyniemi A., 2004, THESIS
[7]   A high-resolution time-to-digital converter implemented in field-programmable-gate-arrays [J].
Song, J ;
An, Q ;
Liu, SB .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2006, 53 (01) :236-241
[8]   Interpolating time counter with 100 ps resolution on a single FPGA device [J].
Szplet, R ;
Kalisz, J ;
Szymanowski, R .
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2000, 49 (04) :879-883
[9]  
Zhang Y., 2006, P 15 INT LAS RANG WO