SIMULATION-BASED DESIGN OF PROGRAMMABLE SYSTOLIC ARRAYS

The paper describes how a simulator is used interactively to design programmable systolic arrays for use in signal-processing applications. A preliminary architecture is defined, with the algorithms targeted for implementation as the starting point. Hardware resources such as maths chips, controllers and memory are then selected. These hardware resources impose constraints on the design. The goal is then that of implementing the desired architecture using the selected hardware. A simulator is described that is used to model and examine architectural and algorithmic options. Via this analysis of the architecture and algorithms, the design can be optimized for a set of applications. The use of the simulator in an actual design is discussed.