AN ARCHITECTURE AND AN ALGORITHM FOR FULLY DIGITAL CORRECTION OF MONOLITHIC PIPELINED ADCS

Accurate trimming of the analog circuitry in analog/digital converters beyond 12 b is difficult. An alternative approach allows a margin of errors on all analog components and compensates for it in the digital domain, This paper describes such a method for pipelined or cyclic converters, Unlike in sigma-delta converters, no over-sampling is required, A powerful identification algorithm determines a limited number of digital coefficients, that linearize the response, Na external measurement hardware is needed. Based on the known performance of state-of-the-art analog blocks, linearity of 16 b at multi-Mhz sampling rates seems achievable.