ON OPTIMIZING VLSI TESTING FOR PRODUCT QUALITY USING DIE-YIELD PREDICTION

被引：23

作者：

SINGH, AD ^{[1
]}

KRISHNA, CM ^{[1
]}

机构：

[1] UNIV MASSACHUSETTS,DEPT ELECT & COMP ENGN,AMHERST,MA 01003

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1993年 / 12卷 / 05期

基金：

美国国家科学基金会;

关键词：

Adaptive systems - Costs - Defects - Integrated circuit testing - Optimization - Quality control;

D O I：

10.1109/43.277614

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes a new adaptive testing procedure that uses spatial defect clustering information, and the available test results for neighboring dies to optimize test costs for VLSI testing. For the same average test costs, our approach shows the potential for better than a factor-of-two improvement in average defect levels. Perhaps more significantly, it also allows the separation of high-quality circuits with defect levels more than an order of magnitude better than the average for the production run. Our proposal is orthogonal to all other approaches for improving defect levels and can be combined with them.

引用

页码：695 / 709

页数：15

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