Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

被引：17
作者：
Vaddi, Ramesh [1 ]
Dasgupta, S. [1 ]
Agarwal, R. P. [1 ]
机构：
[1] Indian Inst Technol, SDVT Grp, Dept Elect & Comp Engn E&CE, Roorkee 247667, Uttarakhand, India
来源：
VLSI DESIGN | 2009年
关键词：
D O I：
10.1155/2009/283702
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In recent years, subthreshold operation has gained a lot of attention clue to ultra low-power consumption in applications requiring low to medium performance. It has also been shown that by optimizing the device structure, power consumption of digital-subthreshold logic can be further minimized while improving its performance. Therefore, subthreshold circuit design is very promising for future ultra low-energy sensor applications as well as high-performance parallel processing. This paper deals with various device and circuit design challenges associated with the state of the art in optimal digital subthreshold circuit design and reviews device design methodologies and circuit topologies for optimal digital-subthreshold operation. This paper identifies the suitable candidates for subthreshold operation at device and circuit levels for optimal subthreshold circuit design and provides an effective roadmap for digital designers interested to work with ultra low-power applications. Copyright (C) 2009 Ramesh Vaddi et al.
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页数：14
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