CACHE COHERENCE PROTOCOLS - EVALUATION USING A MULTIPROCESSOR SIMULATION-MODEL

被引：175
作者：
ARCHIBALD, J
BAER, JL
机构：
来源：
ACM TRANSACTIONS ON COMPUTER SYSTEMS | 1986年 / 4卷 / 04期
关键词：
D O I：
10.1145/6513.6514
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
引用
收藏
页码：273 / 298
页数：26
相关论文
共 16 条
[1]  
Archibald J., 1984, 11th Annual International Symposium on Computer Architecture. Conference Proceedings (Cat. No. 84CH2051-1), P355, DOI 10.1145/800015.808205
[2]  
CENSIER LM, 1978, IEEE T COMPUT, V27, P1112
[3]  
DUBOIS M, 1982, IEEE T COMPUT, V31, P1083, DOI 10.1109/TC.1982.1675925
[4]  
FIELLAND G, 1984, ELECTRONICS DESI SEP, P153
[5]  
FRANK SJ, 1984, ELECTRONICS, V57, P164
[6]  
Goodman J. R., 1983, 10th Annual International Conference on Computer Architecture Conference Proceedings, P124, DOI 10.1145/800046.801647
[7]  
GOODMAN JR, 1986, J VLSI COMPUT SYST, V2
[8]  
Katz R. H., 1985, 12th Annual International Symposium on Computer Architecture Conference Proceedings (Cat. No. 85CH2144-4), P276
[9]  
McCreight E., 1984, DRAGON COMPUTER SYST
[10]  
Papamarcos M. S., 1984, 11th Annual International Symposium on Computer Architecture. Conference Proceedings (Cat. No. 84CH2051-1), P348, DOI 10.1145/800015.808204
12