AN OPTIMIZATION TECHNIQUE FOR THE DESIGN OF MULTIPLE-VALUED PLAS

被引：2
作者：
ASARI, KV
ESWARAN, C
机构：
[1] Department of Electrical Engineering, Indian Institute of Technology, Madras
来源：
IEEE TRANSACTIONS ON COMPUTERS | 1994年 / 43卷 / 01期
关键词：
ADDER; MINIMIZATION; MULTIPLE FUNCTION LITERALS; MULTIPLE VALUED LOGIC; OUTPUT ENCODING; PLA;
D O I：
10.1109/12.250617
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Am optimization technique for the design of two types of multiple-valued PLA's is described in this correspondence. In type-I PLA, the multiple-valued function is realized directly, whereas in type-II PLA, output encoding is used to encode the binary output of the PLA. In both types, multiple function literal circuits are used for the purpose of minimization. It is shown that the proposed technique leads to a considerably reduced size of PIA when compared to the earlier techniques.
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收藏
页码：118 / 122
页数：5
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