SCALING THEORY FOR DOUBLE-GATE SOI MOSFETS

被引：427
|
作者：
SUZUKI, K
TANAKA, T
TOSAKA, Y
HORIE, H
ARIMOTO, Y
机构：
[1] Fujitsu Laboratories Ltd., Atsugi, 243-01
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 1993年 / 40卷 / 12期
关键词：
D O I：
10.1109/16.249482
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We established a scaling theory for double-gate SOI MOSFET's, which gives a guidance for the device design (silicon thickness t(si); gate oxide thickness t(ox)) so that maintaining a subthreshold factor for a given gate length L(G). According to our theory, a device can be designed with a gate length of less than O.l mu m while maintaining the ideal subthreshold factor, which is verified numerically with a two-dimensional device simulator.
引用
收藏
页码：2326 / 2329
页数：4
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