VLSI IMPLEMENTATION OF RESIDUE ADDERS BASED ON BINARY ADDERS

The need for fast computation of digital signal processing algorithms and the development of VLSI techniques of fabrication have motivated the development of efficient hardware implementations of residue number system (RNS) arithmetic. This paper describes the implementation of RNS adders based on binary adders. These adders use two cycles of addition and support any class of modulus. A technique for choosing the correct sum in a two-cycle residue addition is presented and proved correct. Three VLSI layout approaches for residue adders are described and performance figures for area and speed are given. The two approaches using one binary adder offer savings of about 30% in area and significant improvement in speed/area product over the approach using two binary adders.