IMPLEMENTATION OF A FFT RADIX 2 BUTTERFLY USING SERIAL RSFQ MULTIPLIER-ADDERS

We have designed a Decimation-in-Time (DIT) Radix 2 Butterfly integrated circuit. This circuit will be used to implement the 32-point Fast Fourier Transform (FFT) in a parallel data flow architecture. The radix 2 butterfly circuit uses serial RSFQ math and consists of four single bit-wide serial multipliers and eight carry-save serial adders. The circuit with 16-bit wordlength employs only 3400 junctions, occupies an area of 3.8 x 2.0 mm(2), and dissipates less than 1.1 mW power. The multiplier is implemented using the unique RSFQ bit-clock-pipelined schema. We have successfully tested a library of serial multiply-add elements: the 8-bit multiplier at 6.3 GHz and adders with dc bias margin +/-20%. Finally, we have demonstrated full operation of the radix 2 butterfly chip with 5-bit word length.