A 20 BIT LOGARITHMIC NUMBER SYSTEM PROCESSOR

被引：66

作者：

TAYLOR, FJ ^{[1
]}

GILL, R ^{[1
]}

JOSEPH, J ^{[1
]}

RADKE, J ^{[1
]}

机构：

[1] HONEYWELL INC,CTR SYST & RES,MINNEAPOLIS,MN 55440

来源：

IEEE TRANSACTIONS ON COMPUTERS | 1988年 / 37卷 / 02期

关键词：

LOGIC CIRCUITS - SIGNAL PROCESSING - Digital Techniques;

D O I：

10.1109/12.2148

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The architecture and performance of a 20-bit arithmetic processor based on the logarithmic number system (LNS) is described. The processor performs LNS multiplication and division rapidly and with a low hardware complexity. Addition and subtraction in the LNS require the support of a table lookup unit. A scheme is proposed to minimize this complexity using a partitioned memory (ROM) and a PLA (programmable logic array). For performance evaluation, the target technology is integrated Schottky logic. The processor is shown to compare well with, if not to outperform, existing floating point (FLP) processors of equivalent range and precision. The speed-power-product ratio of an equivalent FLP processor, compared to the LNS processor, is reported to be 20 to 1 in the case of the square and square-root operations and 1 to 1 in the case of addition and subtraction. For multiplication and division, this ratio is about 5 to 1.

引用

页码：190 / 200

页数：11