A self-timed 16 * 16 bit fully pipelined multiplier developed in 1.0 pm CMOS technology is described. The circuit is implemented in a new dynamic CMOS family called LDPL (latched differential pass transistor logic). A distinctive mark of LDPL is that its gates operate with pass transistors and integrate the data storage into its output buffer by a cut-off transistor. By using the pass transistor technique LDPL offers a smaller delay time in fully pipelined systems. The LDPL block's nMOS tree evaluates at the same time as the handshake element. Therefore only one node is discharged in the computation phase independent of the implemented logic function. The self-timed multiplier implemented in LDPL achieves a clock rate of 156 MHz. The 16 bit vector merging adder is implemented in 4 pipeline stages by an implementation of manchester chain adders combined with the carry select technique. The vector merging adder only requires 16% of the area of the multiplier (2.59mm(2)). Among the compared asynchronous clocked implementations the LDPL-version offers best relative values in clock rate, efficiency, power consumption and power-delay product.
