Automated Formal Verification of Fault Tolerance for Circuits

被引：0

作者：

Fey, Gorschwin ^{[1
]}

Sulflow, Andre ^{[1
]}

Frehse, Stefan ^{[1
]}

Drechsler, Rolf ^{[1
]}

机构：

[1] Univ Bremen, Bibliothekstr 1, D-28359 Bremen, Germany

来源：

IT-INFORMATION TECHNOLOGY | 2010年 / 52卷 / 04期

关键词：

B.7 [Hardware: Integrated Circuits; B.8.1 [Hardware: Performance and Reliability: Reliability; Testing; and Fault-Tolerance;

D O I：

10.1524/itit.2010.0594

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Continuously shrinking feature sizes lead to an increasing vulnerability of digital circuits. Manufacturing failures, transient faults, or induced bit-flips may tamper the functionality. Thus, analyzing the fault tolerance of a given implementation becomes an important step in the design process. In this work we present a formal method to compute fault tolerance with respect to single soft errors. Extensions are proposed to increase the accuracy, to improve the run time, and to cope with multiple faults.

引用

页码：216 / 223

页数：8

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