50GBIT/S TIME-DIVISION MULTIPLEXER IN SI-BIPOLAR TECHNOLOGY

被引：9

作者：

MOLLER, M ^{[1
]}

REIN, HM ^{[1
]}

FELDER, A ^{[1
]}

POPP, J ^{[1
]}

BOCK, J ^{[1
]}

机构：

[1] SIEMENS AG,CORP RES & DEV,D-81730 MUNICH,GERMANY

来源：

ELECTRONICS LETTERS | 1995年 / 31卷 / 17期

关键词：

TIME DIVISION MULTIPLEXING; MULTIPLEXING; BIPOLAR INTEGRATED CIRCUITS;

D O I：

10.1049/el:19950971

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 2:1 time-division multiplexer is presented which operates up to 50 Gbit/s. This is the highest data rate ever achieved by an integrated circuit in any technology. The output voltage swing is 1 V peak-to-peak at 40 Gbit/s and 0.6 V peak-to-peak at 50 Gbit/s (at 50 Omega on-chip matching). The chips were fabricated in an advanced Si-bipolar technology (f(T) = 35 GHz) and mounted on a comparatively simple measuring socket.

引用

页码：1431 / 1433

页数：3

共 8 条

[1]

BUSSMANN M, 1993, FEB IEEE INT SOL STA, P152

[2] 25 GBIT/S DECISION CIRCUIT, 34 GBIT/S MULTIPLEXER, AND 40 GBIT/S DEMULTIPLEXER IC IN SELECTIVE EPITAXIAL SI BIPOLAR TECHNOLOGY [J].