A RADIX-4 MODULAR MULTIPLICATION HARDWARE ALGORITHM FOR MODULAR EXPONENTIATION

被引:37
作者
TAKAGI, N
机构
[1] Department of Information Science, Kyoto University, Kyoto
关键词
COMPUTER ARITHMETIC; COMPUTER CRYPTOGRAPH; HARDWARE ALGORITHM; MODULAR MULTIPLICATION; REDUNDANT REPRESENTATION; VLSI;
D O I
10.1109/12.156537
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A fast radix-4 modular multiplication hardware algorithm is proposed. It is efficient for modular exponentiation with a large modulus used in public-key cryptosystems such as RSA cryptosystem. The operands and the result of multiplication which are intermediate results in modular exponentiation are represented in a redundant representation. The computation proceeds in serial-parallel fashion. Each subtraction for the division for residue calculation is embedded in the repeated multiply-addition. Each intermediate result is represented in a more redundant representation than that for the operands and the result, so that the number of the required addition/subtractions is reduced. All addition/subtractions are carried out without carry propagation. The algorithm is efficient for modular exponentiation, because only one carry propagate addition is required in the whole computation for a modular exponentiation. A serial-parallel modular multiplier based on the algorithm has a regular cellular array structure with a bit slice feature and is suitable for VLSI implementation. It seems easy to fabricate an RSA chip based on the multiplier using today's technology, which is expected to have a throughput of several times as large as that of the fastest actual RSA chip.
引用
收藏
页码:949 / 956
页数:8
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