A THEORY FOR THE DESIGN OF SOFT-ERROR-TOLERANT VLSI CIRCUITS

被引：2
|
作者：
SAVARIA, Y
HAYES, JF
RUMIN, NC
AGARWAL, VK
机构：
[1] MCGILL UNIV,DEPT ELECT ENGN,MONTREAL H3A 2T5,QUEBEC,CANADA
[2] CONCORDIA UNIV,DEPT ELECT ENGN,MONTREAL H3G 1M8,QUEBEC,CANADA
来源：
IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS | 1986年 / 4卷 / 01期
关键词：
D O I：
10.1109/JSAC.1986.1146297
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：15 / 23
页数：9
相关论文
共 50 条
  • [1] Clock Skew Scheduling for Soft-Error-Tolerant Sequential Circuits
    Wu, Kai-Chiang
    Marculescu, Diana
    2010 DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2010), 2010, : 717 - 722
  • [2] DMBF: Design Metrics Balancing Framework for Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization
    Li, Yan
    Chen, Chao
    Cheng, Xu
    Han, Jun
    Zeng, Xiaoyang
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2023, 70 (10) : 4015 - 4027
  • [3] Soft-Error-Tolerant Design Methodology for Balancing Performance, Power, and Reliability
    Chou, Hsuan-Ming
    Hsiao, Ming-Yi
    Chen, Yi-Chiao
    Yang, Keng-Hao
    Tsao, Jean
    Lung, Chiao-Ling
    Chang, Shih-Chieh
    Jone, Wen-Ben
    Chen, Tien-Fu
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 23 (09) : 1628 - 1639
  • [4] Construction of BILBO FF with Soft-Error-Tolerant Capability
    Namba, Kazuteru
    Ito, Hideo
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2011, E94D (05): : 1045 - 1050
  • [5] Temperature-Insensitive Soft-Error-Tolerant Flip-Flop Design For Automotive Electronics
    Yee, Ralf E. -H.
    Su, Nicholas Y. -J.
    Wang, Lowry P. -T.
    Wen, Charles H. -P.
    Chiueh, Herming
    2024 IEEE 42ND VLSI TEST SYMPOSIUM, VTS 2024, 2024,
  • [6] Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability
    Ruan, Shuangyu
    Namba, Kazuteru
    Ito, Hideo
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2009, E92D (08): : 1534 - 1541
  • [7] Soft-Error-Tolerant Ultralow-Leakage 12T SRAM Bitcell Design
    Jiang, Jianwei
    Lin, Dianpeng
    Xiao, Jun
    Zou, Shichang
    17TH IEEE INTERNATIONAL CONFERENCE ON IC DESIGN AND TECHNOLOGY (ICICDT 2019), 2019,
  • [8] Structural DMR: A Technique for Implementation of Soft-Error-Tolerant FIR Filters
    Reviriego, Pedro
    Bleakley, Chris J.
    Antonio Maestro, Juan
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2011, 58 (08) : 512 - 516
  • [9] High speed soft-error-tolerant latch and flip-flop design for multiple VDD circuit
    Lin, Saihua
    Yang, Huazhong
    Luo, Rong
    IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES, 2007, : 273 - +
  • [10] Feedback-Based Low-Power Soft-Error-Tolerant Design for Dual-Modular Redundancy
    Li, Yan
    Li, Yufeng
    Jie, Han
    Hu, Jianhao
    Yang, Fan
    Zeng, Xuan
    Cockburn, Bruce
    Chen, Jie
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018, 26 (08) : 1585 - 1589
12345