THE TRIPTYCH FPGA ARCHITECTURE

被引：25

作者：

BORRIELLO, G

EBELING, C

HAUCK, SA

BURNS, S

机构：

[1] Department of Computer Science and Engineering, University of Washington, Seattle

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 1995年 / 3卷 / 04期

基金：

美国国家科学基金会;

关键词：

D O I：

10.1109/92.475968

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Field-programmable gate arrays (FPGA's) are an important implementation medium for digital logic, Unfortunately, they currently suffer from poor silicon area utilization due to routing constraints, In this paper we present Triptych, an FPGA architecture designed to achieve improved logic density with competitive performance, This is done by allowing a permapping tradeoff between logic and routing resources, and with a routing scheme designed to match the structure of typical circuits, We show that, using manual placement, this architecture yields a logic density improvement of up to a factor of 3.5 over commercial FPGA's, with comparable performance, We also describe Montage, the first FPGA architecture to fully support asynchronous and synchronous interface circuits.

引用

页码：491 / 501

页数：11