ANALYSIS OF INTERCONNECTION DELAY ON VERY HIGH-SPEED LSI VLSI CHIPS USING AN MIS MICROSTRIP LINE MODEL

被引：23

作者：

HASEGAWA, H

SEKI, S

机构：

来源：

关键词：

D O I：

10.1109/TMTT.1984.1132921

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：1721 / 1727

页数：7

共 25 条

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[24] A SIMPLE FORMULA FOR THE ESTIMATION OF THE CAPACITANCE OF TWO-DIMENSIONAL INTERCONNECTS IN VLSI CIRCUITS
YUAN, CP
TRICK, TN
[J]. ELECTRON DEVICE LETTERS, 1982, 3 (12): : 391 - 393
[25] YUAN HT, 1982, IEEE T ELECTRON DEV, V29, P639