PMOS INTEGRATED-CIRCUIT FABRICATION USING BF3 PLASMA IMMERSION ION-IMPLANTATION

The feasibility of plasma immersion ion implantation (PIII) for multi-implant integrated circuit fabrication is demonstrated. Patterned Si wafers were immersed in a BF3 plasma for p-type doping steps. Boron implants of up to 3 x 10(15) atoms/cm2 were achieved by applying microsecond negative voltage (-2 to -30 kV) pulses to the wafers at a frequency of 100 Hz to 1 kHz. After implantation the wafers were annealed using rapid thermal annealing (RTA) at 1060-degrees-C for 20 sec to activate the dopants and to recrystallize the implant damaged Si. For the PMOS process sequence both the Si source-drain and polycrystalline Si (poly-Si) gate doping steps were performed using PIII. The functionality of several types of devices, including diodes, capacitors, and transistors, were electrically measured to evaluate the compatibility of PIII with MOS process integration.