This paper compares the error-rate performance and circuit complexity of Fixed-Delay Tree Search with Decision-Feedback (FDTS/DF) to that of Class IV Partial Response Equalization followed by Viterbi Detection (PR4-ML). The impact of realistic impulse responses, mis-equalization, phase errors, and offtrack interference on both detection strategies is explored. Two computationally efficient methods for implementing FDTS/DF are presented. These FDTS/DF architectures avoid explicit multiplication - one uses a RAM-based table lookup and the other uses binary equalization over the tree-depth.