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- [44] Load and logic co-optimization for design of soft-error resistant nanometer CMOS circuits 11TH IEEE INTERNATIONAL ON-LINE TESTING SYMPOSIUM, 2005, : 35 - 40
- [47] On Antagonism Between Side-Channel Security and Soft-Error Reliability in BNN Inference Engines PROCEEDINGS OF THE 2021 IFIP/IEEE INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC), 2021, : 84 - 89
- [50] Analytical approach for soft error rate estimation in digital circuits 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 2991 - 2994