METASTABILITY OF CMOS MASTER SLAVE FLIP-FLOPS

被引:17
作者
GABARA, TJ [1 ]
CYR, GJ [1 ]
STROUD, CE [1 ]
机构
[1] AT&T BELL LABS,NAPERVILLE,IL 60566
来源
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 1992年 / 39卷 / 10期
关键词
D O I
10.1109/82.199899
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents circuit techniques used to improve the mean time between failures (MTBF) of a latch due to metastable events. The complete approach includes a unique design of the latch and the formation of series connected master/slave (M/S) flip-flops using this latch. An equation is developed to predict the MTBF due to metastability of a single latch and is extended to include single and multiple series connected M/S flip-flops. The equation predicts that the MTBF increases significantly by using such a M/S flip-flop configuration.
引用
收藏
页码:734 / 740
页数:7
相关论文
共 10 条
[1]  
HOHL J, 1984, IEEE J SOLID STATE C, V19, P26
[2]   METASTABILITY BEHAVIOR OF CMOS ASIC FLIP-FLOPS IN THEORY AND TEST [J].
HORSTMANN, JU ;
EICHEL, HW ;
COATES, RL .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (01) :146-157
[3]  
KLEEMAN L, 1987, IEEE DES TEST COMPUT, V5, P4
[4]  
LEUNG CW, 1988, MAY CICC
[5]  
NAGEL LW, 1980, 1980 P INT S CIRC SY
[6]  
NOOTBAAR K, 1990, EDN SEP, P141
[7]  
SAKURAI T, 1988, IEEE J SOLID STATE C, V2, P901
[8]  
STOLL PA, 1982, VLSI DESIGN, V3, P56
[9]  
THOMPSON DW, 1991, FEB ISSCC
[10]  
VEENDRICK HJM, 1980, IEEE J SOLID STATE C, V15