EFFECTIVENESS OF PRIVATE CACHES IN MULTIPROCESSOR SYSTEMS WITH PARALLEL-PIPELINED MEMORIES

被引:0
|
作者
BRIGGS, FA [1 ]
DUBOIS, M [1 ]
机构
[1] THOMSON CSF,LCR DOMAINE CORBEVILLE,F-91401 ORSAY,FRANCE
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
引用
收藏
页码:48 / 59
页数:12
相关论文
共 50 条
  • [1] ORGANIZATION OF SEMICONDUCTOR MEMORIES FOR PARALLEL-PIPELINED PROCESSORS
    BRIGGS, FA
    DAVIDSON, ES
    IEEE TRANSACTIONS ON COMPUTERS, 1977, 26 (02) : 162 - 169
  • [2] VECTOR COMPUTATIONS ON A PARALLEL-PIPELINED PROCESSOR
    IGNATUSHCHENKO, VV
    KOGAN, YA
    SIGNAEVSKII, VA
    AUTOMATION AND REMOTE CONTROL, 1982, 43 (09) : 1202 - 1212
  • [3] Efficient Parallel-Pipelined GHASH for Message Authentication
    Abdellatif, Karim M.
    Chotin-Avot, R.
    Mehrez, H.
    2012 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG), 2012,
  • [4] SCHEDULING TREES IN PARALLEL-PIPELINED PROCESSING ENVIRONMENTS
    LI, HF
    IEEE TRANSACTIONS ON COMPUTERS, 1977, 26 (11) : 1101 - 1112
  • [5] Parallel-pipelined architecture for the Kalman based adaptive equalizer
    Santha, Kr.
    Vaidehi, V.
    2007 International Conference of Signal Processing, Communications and Networking, Vols 1 and 2, 2006, : 172 - 177
  • [6] Analytical model for a multiprocessor with private caches and shared memory
    Nikolov, Angel Vassilev
    INTERNATIONAL JOURNAL OF COMPUTERS COMMUNICATIONS & CONTROL, 2008, 3 (02) : 172 - 182
  • [7] Parallel-pipelined architecture for 2-D ICT VLSI implementation
    Michell, JA
    Ruiz, GA
    Burón, AM
    2003 INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, VOL 3, PROCEEDINGS, 2003, : 89 - 92
  • [8] An Algorithm for Parallel Execution of Loops in Chip Multiprocessor Caches
    Subha, S.
    2009 INTERNATIONAL CONFERENCE ON ADVANCES IN RECENT TECHNOLOGIES IN COMMUNICATION AND COMPUTING (ARTCOM 2009), 2009, : 85 - 89
  • [9] A Novel Low-Overhead Fault Tolerant Parallel-Pipelined FFT Design
    Xie, Yu
    Yang, Chen
    Mao, Chuang-An
    Chen, He
    Xie, Yi-Zhuang
    2017 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFT), 2017, : 155 - 158
  • [10] Parallel-pipelined architecture of H.264 deblocking filter with adaptive dynamic power
    Wei H.
    Lin T.
    Journal of Shanghai Jiaotong University (Science), 2010, 15 (2) : 224 - 230