FAULT TOLERANCE IN VLSI CIRCUITS

被引:42
作者
KOREN, I
SINGH, AD
机构
[1] Dept. of Electrical and Computer Engineering, University of Massachusetts, Amherst
基金
美国国家科学基金会;
关键词
D O I
10.1109/2.56854
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
[No abstract available]
引用
收藏
页码:73 / 83
页数:11
相关论文
共 21 条
[1]   A TAXONOMY OF RECONFIGURATION TECHNIQUES FOR FAULT-TOLERANT PROCESSOR ARRAYS [J].
CHEAN, M ;
FORTES, JAB .
COMPUTER, 1990, 23 (01) :55-69
[2]  
FUCHS WK, 1989, DEFECT FAULT TOLERAN, V1, P213
[3]  
Koren I., 1981, 8th Annual Symposium on Computer Architecture, P425
[4]  
Koren I., 1988, Yield Modelling and Defect Tolerance in VLSI, P91
[5]  
KOREN I, 1989, DEFECT FAULT TOLERAN, V1, P1
[6]  
KOREN I, 1988, IEEE J SOLID STA JUN, P859
[7]  
LEVELUGLE R, 1989, DEFECT FAULT TOLERAN, V1, P179
[8]  
Maly W., 1988, Yield Modelling and Defect Tolerance in VLSI, P3
[9]   THE TRIALS OF WAFER-SCALE INTEGRATION [J].
MCDONALD, JF ;
ROGERS, EH ;
ROSE, K ;
STECKL, AJ .
IEEE SPECTRUM, 1984, 21 (10) :32-39
[10]   A REVIEW OF FAULT-TOLERANT TECHNIQUES FOR THE ENHANCEMENT OF INTEGRATED-CIRCUIT YIELD [J].
MOORE, WR .
PROCEEDINGS OF THE IEEE, 1986, 74 (05) :684-698