A DESIGN METHOD FOR ONLINE RECONFIGURABLE ARRAY PROCESSORS

In this paper a design methodology for reconfigurable array processors is described. It extends a known design method for nonredundant array architectures, which is based upon an algorithm description. Using self-checking processing elements, the systematic design of on-line reconfigurable arrays is feasible, which perform reconfiguration concurrently with data processing. Reconfiguration schemes suitable for array processors with arbitrary dimension are presented. One reconfiguration scheme addresses arrays with high probability of both dynanmic and static faults. They are treated differently to reduce hardware overhead. A systematic approach for reliability estimation based on a model including dynamic and static faults is discussed. The design method is applied to matrix-matrix-multiplication. Estimations of hardware overhead are given.