SEQUENTIAL HARDWARE PREFETCHING IN SHARED-MEMORY MULTIPROCESSORS

被引：70

作者：

DAHLGREN, F ^{[1
]}

DUBOIS, M ^{[1
]}

STENSTROM, P ^{[1
]}

机构：

[1] UNIV SO CALIF, DEPT ELECT ENGN SYST, LOS ANGELES, CA 90089 USA

来源：

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS | 1995年 / 6卷 / 07期

基金：

美国国家科学基金会;

关键词：

HARDWARE-CONTROLLED PREFETCHING; LATENCY TOLERANCE; MEMORY CONSISTENCY MODELS; PERFORMANCE EVALUATION; SEQUENTIAL PREFETCHING; SHARED-MEMORY MULTIPROCESSORS;

D O I：

10.1109/71.395402

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

To offset the effect of read miss penalties on processor utilization in shared-memory multiprocessors, several software- and hardware-based data prefetching schemes have been proposed, A major advantage of hardware techniques is that they need no support from the programmer or compiler. Sequential prefetching is a simple hardware-controlled prefetching technique which relies on the automatic prefetch of consecutive blocks following the block that misses in the cache, thus exploiting spatial locality. In its simplest form, the number of prefetched blocks: on each miss Is fixed throughout the execution, However, since the prefetching efficiency varies during the execution of a program, we propose to adapt the number of prefetched blocks according to a dynamic measure of prefetching effectiveness, Simulations of this adaptive scheme show reductions of the number of read misses, the read penalty, and of the execution time by up to 78%, 58%, and 25% respectively,

引用

页码：733 / 746

页数：14

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