Design of a high-performance PJFET for the input stage of an integrated operational amplifier

被引：1

作者：

Shui, Guohua ^{[1
]}

Tang, Zhaohuan ^{[1
]}

Wang, Zhikuan ^{[1
]}

Ou, Hongqi ^{[1
,2
]}

Yang, Yonghui ^{[1
,2
]}

Liu Yong ^{[1
,2
]}

Wang, Xueyi ^{[1
]}

机构：

[1] Sichuan Inst Solid State Circuits, CETC, Chongqing 400060, Peoples R China

[2] Natl Lab Analog ICs, Chongqing 400060, Peoples R China

来源：

JOURNAL OF SEMICONDUCTORS | 2010年 / 31卷 / 01期

关键词：

PJFET; operational amplifier; Bi-FET process; ultra-shallow junction; high input-impedance;

D O I：

10.1088/1674-4926/31/1/014004

中图分类号：

O469 [凝聚态物理学];

学科分类号：

070205 ;

摘要：

With Shockley's approximate-channel theory and TCAD tools, a high-voltage, ultra-shallow junction PJFET for the input stage of an integrated operational amplifier (OPA) was realized. The high-performance PJFET device was developed in the Bi-FET process technology. The measured specifications are as follows. The top-gate junction depth is about 0.1 mu m, the gate-leakage current is less than 5 pA, the breakdown voltage is more than 80 V, and the pinch-off voltage is optional between 0.8 and 2.0 V. The device and its Bi-FET process technology were used to design and process a high input-impedance integrated OPA. The measured results show that the OPA has a bias current of less than 50 pA, voltage noise of less than 50 nV/Hz(1/2), and current noise of less than 0.05 pA/Hz(1/2).

引用

页数：5

共 27 条

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