A FUZZY-LOGIC INFERENCE PROCESSOR

被引：31

作者：

FATTARUSO, JW ^{[1
]}

MAHANTSHETTI, SS ^{[1
]}

BARTON, JB ^{[1
]}

机构：

[1] UNIV CALIF BERKELEY,BERKELEY,CA 94720

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1994年 / 29卷 / 04期

关键词：

Center of mass defuzzification - Fuzzy logic inference processor - Memory locations;

D O I：

10.1109/4.280687

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A mixed analog-digital fuzzy logic inference engine chip fabricated in an 0.8 mum CMOS process is described. Interface to the processor behaves like a static RAM, and computation of the fuzzy logic inference is performed between memory locations in parallel by an array of analog charge-domain circuits. Eight inputs and four outputs are provided, and up to 32 rules may be programmed into the chip. The results of the inference over all rules, including a center-of-mass defuzzification, may be computed in 2 mus.

引用

页码：397 / 402

页数：6

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