SIMULATION OF ELECTRICAL OVERSTRESS THERMAL FAILURES IN INTEGRATED-CIRCUITS

Electrical overstress (EOS) and electrostatic discharge (ESD) pose the most dominant threats to integrated circuits (IC's) reliability. As a measure for EOS/ESD reliability, the power-to-failure versus time-to-failure relationship (power profile) has been recently proposed to determine the EOS failure thresholds of integrated circuits. This paper presents a nonlinear mixed 2D-1D thermal simulator, iTSIM, for ESD/EOS failure studies in ICs. iTSIM's computational efficiency to handle large-scale EOS thermal problems in IC's derives from the special set of boundary conditions introduced in this paper. Simulated power profiles for various combinations of major thermal parameters of the IC die-package structure are shown to agree with experimental data.