SIMULATION OF ELECTRICAL OVERSTRESS THERMAL FAILURES IN INTEGRATED-CIRCUITS

被引：1

作者：

DIAZ, CH

KANG, SM

DUVVURY, C

机构：

[1] UNIV ILLINOIS,COORDINATED SCI LAB,URBANA,IL 61801

[2] TEXAS INSTRUMENTS INC,CTR SEMICOND PROC & DESIGN,DALLAS,TX 75265

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1994年 / 41卷 / 03期

关键词：

Computational complexity - Computational methods - Electric discharges - Electrostatics - Failure analysis - Integrated circuit layout - Overcurrent protection - Overvoltage protection - Semiconductor device models - Semiconductor device structures - Thermodynamic properties;

D O I：

10.1109/16.275221

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Electrical overstress (EOS) and electrostatic discharge (ESD) pose the most dominant threats to integrated circuits (IC's) reliability. As a measure for EOS/ESD reliability, the power-to-failure versus time-to-failure relationship (power profile) has been recently proposed to determine the EOS failure thresholds of integrated circuits. This paper presents a nonlinear mixed 2D-1D thermal simulator, iTSIM, for ESD/EOS failure studies in ICs. iTSIM's computational efficiency to handle large-scale EOS thermal problems in IC's derives from the special set of boundary conditions introduced in this paper. Simulated power profiles for various combinations of major thermal parameters of the IC die-package structure are shown to agree with experimental data.

引用

页码：359 / 366

页数：8

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