GRAPH MODELS FOR PLA FOLDING PROBLEMS

被引：1
|
作者：
MACII, E
WOLF, T
机构：
[1] POLITECN TORINO, DIPARTIMENTO AUTOMAT & INFORMAT, I-10129 TURIN, ITALY
[2] UNIV CALIF LOS ANGELES, DEPT ELECT ENGN, LOS ANGELES, CA 90024 USA
来源：
INTERNATIONAL JOURNAL OF SYSTEMS SCIENCE | 1995年 / 26卷 / 07期
关键词：
D O I：
10.1080/00207729508929110
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper considers combinatorial optimization models for the problem of reducing the chip area of programmable logic arrays (PLAs) by folding. In particular, we focus on the variable and block folding problems, and we present theoretical optimization models based on the compatibility graph, on the incompatibility graph and on the representative hyper-graph of a PLA.
引用
收藏
页码：1439 / 1445
页数：7
相关论文
共 50 条
12345