A SCARCE-STATE-TRANSITION VITERBI-DECODER VLSI FOR BIT ERROR CORRECTION

被引：19
作者：
ISHITANI, T
TANSHO, K
MIYAHARA, N
KUBOTA, S
KATO, S
机构：
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1987年 / 22卷 / 04期
关键词：
D O I：
10.1109/JSSC.1987.1052775
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：575 / 582
页数：8
相关论文
共 14 条
[1]  
ADACHI T, 1982, 19TH P DES AUT C, P785
[2]  
Bhargava V. K., 1981, DIGITAL COMMUNICATIO
[3]   VITERBI DECODING FOR SATELLITE AND SPACE COMMUNICATION [J].
HELLER, JA ;
JACOBS, IM .
IEEE TRANSACTIONS ON COMMUNICATION TECHNOLOGY, 1971, CO19 (05) :835-&
[4]  
HOPPES PEC, 1982, FEB ISSCC, P28
[5]   AN INTEGRATED MODULAR AND STANDARD CELL VLSI DESIGN APPROACH [J].
KASAI, R ;
FUKAMI, K ;
TANSHO, K ;
KITAZAWA, H ;
HORIGUCHI, S .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1985, 20 (01) :407-412
[6]  
KITAZAWA H, 1983, MONOGRAPH WORKING GR, V19
[7]  
KITAZAWA H, 1985, P ISCAS 85, P1035
[8]  
KUBOTA S, IN PRESS SCARCE STAT
[9]  
ORNDORFF RM, 1981, NATIONAL TELECOMMUNI
[10]   NEW SYNDROME DECODING TECHNIQUES FOR THE (N,K) CONVOLUTIONAL-CODES [J].
REED, IS ;
TRUONG, TK .
IEE PROCEEDINGS-F RADAR AND SIGNAL PROCESSING, 1984, 131 (04) :412-416
12