Logic synthesis system for engineering changes based on error propagation and re-synthesis algorithm

After the functional/logic design and physical design of an LSI have been completed, there often arises a need to make an engineering change (EC) because of a specification change or the discovery of a logic design error. This paper outlines an EC logic synthesis system and EC logic synthesis algorithm which enable a circuit to be modified to satisfy a new logic specification while preserving its structure as much as possible. This system is designed for circuits of more than one thousand gates and can handle multiple simultaneous changes to the logic specification. Heuristics are used to minimize the number of additional gates introduced by EC logic synthesis. In experiments using real design data, new circuits satisfying new logic specifications with, on average, fewer than 3% additional gates were obtained, and the effectiveness of this system was confirmed.