A SYSTOLIC ARRAY EXPLOITING THE INHERENT PARALLELISMS OF ARTIFICIAL NEURAL NETWORKS

被引：10

作者：

CHUNG, JH ^{[1
]}

YOON, HS ^{[1
]}

MAENG, SR ^{[1
]}

机构：

[1] KOREA ADV INST SCI & TECHNOL,DEPT COMP SCI,TAEJON 305701,SOUTH KOREA

来源：

MICROPROCESSING AND MICROPROGRAMMING | 1992年 / 33卷 / 03期

关键词：

ARTIFICIAL NEURAL NETWORK; BACKPROPAGATION MODEL; SYSTOLIC ARRAY; PIPELINING; VLSI IMPLEMENTATION;

D O I：

10.1016/0165-6074(92)90017-2

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The systolic array implementation of artificial neural networks is one of the best solutions to the communication problems generated by the highly interconnected neurons. In this paper, a two-dimensional systolic array for backpropagation neural network is presented. The design is based on the classical systolic algorithm of matrix-by-vector multiplication, and exploits the inherent parallelisms of backpropagation neural networks. This design executes the forward and backward passes in parallel, and exploits the pipelined parallelism of multiple patterns in each pass. The estimated performance of this design shows that the pipelining of multiple patterns is an important factor in VLSI neural network implementations.

引用

页码：145 / 159

页数：15

共 25 条

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