TARGETING HETEROGENEOUS ARCHITECTURES VIA MACRO DATA FLOW

被引:5
作者
Aldinucci, M. [1 ]
Danelutto, M. [2 ]
Kilpatrick, P. [3 ]
Torquati, M. [4 ]
机构
[1] Univ Turin, Dept Comp Sci, C So Svizzera 185, I-10149 Turin, Italy
[2] Univ Pisa, Dept Comp Sci, I-56127 Pisa, Italy
[3] Queens Univ Belfast, Dept Comp Sci, Belfast BT9 5BN, Antrim, North Ireland
[4] Univ Pisa, Dept Comp Sci, I-56127 Pisa, Italy
关键词
Data flow; structured parallelism; algorithmic skeletons; parallel design patterns; heterogeneous architectures;
D O I
10.1142/S0129626412400063
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
We propose a data flow based run time system as an efficient tool for supporting execution of parallel code on heterogeneous architectures hosting both multicore CPUs and GPUs. We discuss how the proposed run time system may be the target of both structured parallel applications developed using algorithmic skeletons/parallel design patterns and also more "domain specific" programming models. Experimental results demonstrating the feasibility of the approach are presented.
引用
收藏
页数:12
相关论文
共 23 条
[1]  
Aldinucci M., 2012, Proceedings of the 2012 20th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2012), P27, DOI 10.1109/PDP.2012.44
[2]  
Aldinucci M, 2009, EUROMICRO WORKSHOP P, P3, DOI [10.1109/PDP.2009.48, 10.1109/.47]
[3]  
Arandi Samer, 2010, Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS 2010), P152, DOI 10.1109/ICSAMOS.2010.5642072
[4]   The Design of OpenMP Tasks [J].
Ayguade, Eduard ;
Copty, Nawal ;
Duran, Alejandro ;
Hoeflinger, Jay ;
Lin, Yuan ;
Massaioli, Federico ;
Teruel, Xavier ;
Unnikrishnan, Priya ;
Zhang, Guansong .
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2009, 20 (03) :404-418
[5]   P(3)L - A STRUCTURED HIGH-LEVEL PARALLEL LANGUAGE, AND ITS STRUCTURED SUPPORT [J].
BACCI, B ;
DANELUTTO, M ;
ORLANDO, S ;
PELAGATTI, S ;
VANNESCHI, M .
CONCURRENCY-PRACTICE AND EXPERIENCE, 1995, 7 (03) :225-255
[6]  
Badia R., 2012, P HET 2012 IN PRESS
[7]  
Bhattacharyya S. S., 2008, ACMSIGARCH COMPUT AR, V36, P29
[8]  
Cole M, 2004, PARALLEL COMPUT, V30, P389, DOI [10.1016/j.parco.2003.12.002, 10.1016/j.parco.2004.12.002]
[9]  
Dagstgeer U., 2012, P PARCO 201 IN PRESS
[10]  
Danelutto M., 2001, Parallel Processing Letters, V11, P41, DOI 10.1142/S0129626401000415