A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-mu m SOI CMOS technology

被引：6

作者：

Ning, Qiao ^{[1
,2
]}

Zhang Guoquan ^{[2
]}

Bo, Yang ^{[2
]}

Liu Zhongli ^{[2
]}

Fang, Yu ^{[2
]}

机构：

[1] Chinese Acad Sci, Inst Semicond, Beijing 100083, Peoples R China

[2] Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China

来源：

JOURNAL OF SEMICONDUCTORS | 2012年 / 33卷 / 09期

关键词：

successive approximation register; analog-to-digital converter; reference-free; on-chip calibration; energy efficient;

D O I：

10.1088/1674-4926/33/9/095005

中图分类号：

O469 [凝聚态物理学];

学科分类号：

070205 ;

摘要：

A 10-bit 50-MS/s reference-free low power successive approximation register (SAR) analog-to-digital converter (ADC) is presented. An energy efficient switching scheme is utilized in this design to obtain low power and high frequency operation performance without an additional analog power supply or on-chip/off-chip reference. An on-chip calibration DAC (CDAC) is implemented to cancel the offset of the latch-type sense amplifier (SA) to ensure precision whilst getting rid of the dependence on the pre-amplifier, so that the power consumption can be reduced further. The design was fabricated in IBM 0.18-mu m 1P4M SOI CMOS process technology. At a 1.5-V supply and 50-MS/s with 5-MHz input, the ADC achieves an SNDR of 56.76 dB and consumes 1.72 mW, resulting in a figure of merit (FOM) of 61.1 fJ/conversion-step.

引用

页数：9