REAL-TIME IMPLEMENTATION OF THE VSELP ON A 16-BIT DSP CHIP

被引：5
作者：
SUNWOO, MH
PARK, S
机构：
[1] Digital Signal Processor Operations, Motorola, Inc., Austin, Texas
来源：
IEEE TRANSACTIONS ON CONSUMER ELECTRONICS | 1991年 / 37卷 / 04期
关键词：
D O I：
10.1109/30.106939
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a real-time implementation of the Vector Sum-Excited Linear Predictive (VSELP) speech coder which has been chosen as the digital cellular standard in North America and Japan. A real-time implementation of the VSELP algorithm can be realized using a 16-bit general purpose digital signal processor (GPDSP) with on-chip codec. The principles of the VSELP algorithm and the real-time implementation of the algorithm on the GPDSP chip are addressed. The paper also discusses the finite word-length effects and considers possible methods to reduce the effects.
引用
收藏
页码：772 / 782
页数：11
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