JITTER REDUCTION OF A DIGITAL PHASE-LOCKED LOOP

被引：3
|
作者：
YAMASHITA, M [1 ]
TSUJI, T [1 ]
NISHIMURA, T [1 ]
MURATA, M [1 ]
NAMEKAWA, T [1 ]
机构：
[1] OSAKA UNIV,FAC ENGN,DEPT COMMUN ENGN,SUITA,OSAKA 565,JAPAN
来源：
PROCEEDINGS OF THE IEEE | 1976年 / 64卷 / 11期
关键词：
D O I：
10.1109/PROC.1976.10396
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：1640 / 1641
页数：2
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