Implementation of A Optimized Systolic Array Architecture for FSBMA using FPGA for Real-time Applications

In this paper, a optimized systolic array architecture for Full Search Block Matching Algorithm is presented. This Array Architecture is implemented by RTL-level VHDL for using as a motion estimation unit in low bit rate and real-time applications such as video telephony. This implementation is synthesized for two FPGA families, Xilinx Spartan and Virtex, The results for area occupation and maximum operating frequency are presented. This results show that this array architecture is suitable for real-time video encoding systems with minimum hardware utilization and high performance.