SYNCHRONOUS-MODE EVALUATION OF DELAYS IN CMOS STRUCTURES

被引：6
作者：
DESCHACHT, D
ROBERT, M
AUVERGNE, D
机构：
[1] Laboratoire d’Automatique et de Microelectronique de Montpellier, Universite des Sciences et Techniques du Languedoc
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1991年 / 26卷 / 05期
关键词：
D O I：
10.1109/4.78250
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The extension of the explicit formulation of delays in CMOS VLSI to synchronous-mode evaluation allows the accurate evaluation of data-path timing (few percent with respect to SPICE simulation) of general CMOS structures for all available input drive configurations, resulting in fast and real identification of timing problems.
引用
收藏
页码：789 / 795
页数：7
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