SYMBOLIC RELIABILITY EVALUATION USING A MICROPROCESSOR

被引:0
|
作者
SHARMA, S
AGGARWAL, KK
机构
关键词
D O I
10.1016/0951-8320(89)90054-9
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
引用
收藏
页码:51 / 67
页数:17
相关论文
共 50 条
  • [31] Efficient reliability evaluation using spreadsheet
    Low, BK
    Tang, WH
    JOURNAL OF ENGINEERING MECHANICS-ASCE, 1997, 123 (07): : 749 - 752
  • [32] CMOS ROMS FOR MICROPROCESSOR EVALUATION
    PECKOVER, P
    MICROPROCESSORS AND MICROSYSTEMS, 1980, 4 (08) : 303 - 306
  • [33] PERFORMANCE EVALUATION OF MICROPROCESSOR ARRAY
    LI, HF
    LAU, CC
    IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1983, 130 (03): : 65 - 74
  • [34] SYMBOLIC EVALUATION WITH STRUCTURAL RECURSIVE SYMBOLIC CONSTANTS
    GIANNOTTI, F
    MATTEUCCI, A
    PEDRESCHI, D
    TURINI, F
    SCIENCE OF COMPUTER PROGRAMMING, 1987, 9 (02) : 161 - 177
  • [35] SYMBOLIC TESTING AND DISSECT SYMBOLIC EVALUATION SYSTEM
    HOWDEN, WE
    IEEE TRANSACTIONS ON SOFTWARE ENGINEERING, 1977, 3 (04) : 266 - 278
  • [36] Statistical Reliability Estimation of Microprocessor-Based Systems
    Savino, Alessandro
    Di Carlo, Stefano
    Politano, Gianfranco
    Benso, Alfredo
    Bosio, Alberto
    Di Natale, Giorgio
    IEEE TRANSACTIONS ON COMPUTERS, 2012, 61 (11) : 1521 - 1534
  • [37] MICROPROCESSOR TESTING TO IMPROVE MODEM TRANSFORMER RELIABILITY.
    Vancata, Brian J.
    1978, 24 (08): : 45 - 47
  • [38] RELIABILITY-EVALUATIONS OF MICROPROCESSOR SYSTEM WITH WATCHDOG TIMER
    YASUI, K
    NAKAGAWA, T
    HARATA, Y
    ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE, 1995, 78 (04): : 84 - 91
  • [39] Formal verification of memory arrays using symbolic trajectory evaluation
    Pandey, M
    Bryant, RE
    INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN AND TESTING, PROCEEDINGS, 1997, : 42 - 49
  • [40] RELIABILITY OF MICROPROCESSOR-BASED PROTECTIVE DEVICES - REVISITED
    Gurevich, Vladimir
    JOURNAL OF ELECTRICAL ENGINEERING-ELEKTROTECHNICKY CASOPIS, 2009, 60 (05): : 295 - 300