THE LATCHUP RISK OF CMOS-TECHNOLOGY IN SPACE

被引：19

作者：

MOREAU, Y ^{[1
]}

DELAROCHETTE, H ^{[1
]}

BRUGUIER, G ^{[1
]}

GASIOT, J ^{[1
]}

PELANCHON, F ^{[1
]}

SUDRE, C ^{[1
]}

ECOFFET, R ^{[1
]}

机构：

[1] CTR NATL ETUD SPATIALES,F-31055 TOULOUSE,FRANCE

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 1993年 / 40卷 / 06期

关键词：

D O I：

10.1109/23.273473

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The use of CMOS technology in space needs a careful evaluation of the latchup risk. The radiation tolerance is studied here for a standard 1.0 mu m high density technology and its hardened variants. The internal currents and densities are read through dynamic two/three dimensional device simulations, performed on a complete description of the CMOS inverter cell and a simulated heavy ion strike. An evaluation of the capture cross section versus the ion energy is derived from the statististical distribution of ion tracks through the structure.

引用

页码：1831 / 1837

页数：7

共 20 条

[1] SIERRA - A 3-D DEVICE SIMULATOR FOR RELIABILITY MODELING [J].