16X16 BIT PARALLEL MULTIPLIER BASED ON 6K GATE ARRAY WITH 0.3-MU-M ALGAAS GAAS QUANTUM-WELL TRANSISTORS

被引：11

作者：

THIEDE, A

BERROTH, M

HURM, V

NOWOTNY, U

SEIBEL, J

GOTZEINA, W

SEDLER, M

RAYNOR, B

KOEHLER, K

HOFMANN, P

HUELSMANN, A

KAUFEL, G

SCHNEIDER, J

机构：

[1] Fraunhofer-Institute for Applied Solid State Physics, 7800, Freiburg

来源：

ELECTRONICS LETTERS | 1992年 / 28卷 / 11期

关键词：

MULTIPLIERS; INTEGRATED CIRCUITS;

D O I：

10.1049/el:19920639

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

he design and performance of a 16 x 16 bit parallel multiplier based on a 6 K gate array will be presented. This LSI semicustom IC demonstrates the high potential of our AlGaAs/GaAs quantum well FETs with a gate length of 0.3-mu-m. The best multiplication time measured was 7.2 ns.

引用

页码：1005 / 1007

页数：3

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