A 14-bit 50 MS/s sample-and-hold circuit for pipelined ADC

被引：2
|
作者：
Yue Sen [1 ]
Zhao Yiqiang [1 ]
Pang Ruilong [1 ]
Sheng Yun [1 ]
机构：
[1] Tianjin Univ, Sch Elect Informat Engn, Tianjin 300072, Peoples R China
来源：
JOURNAL OF SEMICONDUCTORS | 2014年 / 35卷 / 05期
关键词：
sample/hold circuit; pipeline ADC; gain-boosted OTA; bootstrapped switch;
D O I：
10.1088/1674-4926/35/5/055009
中图分类号：
O469 [凝聚态物理学];
学科分类号：
070205 ;
摘要：
A high performance sample-and-hold (S/H) circuit used in a pipelined analog-to-digital converter (ADC) is presented. Capacitor flip-around architecture is used in this S/H circuit with a novel gain-boosted differential folded cascode operational transconductance amplifier. A double-bootstrapped switch is designed to improve the performance of the circuit. The circuit is implemented using a 0.18 mu m 1P6M CMOS process. Measurement results show that the effective number of bits is 14.03 bits, the spurious free dynamic range is 94.62 dB, the signal to noise and distortion ratio is 86.28 dB, and the total harmonic distortion is 91: 84 dB for a 5 MHz input signal with 50 MS/s sampling rate. A pipeline ADC with the designed S/H circuit has been implemented.
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收藏
页数：6
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