Compact Modelling of High Speed Low Power 10T D-FF Using Nano-Scale Technology

As the compactness of device design increases, the short channel effects are important parameters to take into consideration. In this report, low power adiabatic logic based on FinFET has been suggested. Due to lower leakage current higher on-state current and design flexibility of FinFET, the cared-for logic shows power reduction, performance enhancement and area reduction compared with CMOS logic circuitry. In this newspaper, we designed our circuitry using shorted gate FinFET because shorted gate FinFETs shows better performance than back gate-biased independent gate FinFETs. D flip-flop is used to store a bit or result or state of any part. Device density is more important feature in the digital universe. A proposed circuitry of clocked D Flip-Flop as the test circuit has been demonstrated based on the 45 nm FinFET Technology. The proposed circuit based on FinFET devices achieves a power decrease of up to 75% and as the thickness of the silicon layer between 45 nM-15 nm, electron mobility increases by 25% and more, temperature shows their effect on mobility and power of the circuit, as temperature increases mobility also increases (V = mu E). For the calculation these results we are using cadence tools. In FinFET Technology FIN (width) controls the short channel effect and FIN height controls the drive current, the effective channel width W-eff = 2 * n * FIN (Height). After simulating the circuit, we get values of Average power is 72.07nW and Delay 20.08 E-9 s.