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A 50-MU-A STANDBY 1MX1/256KX4 CMOS DRAM WITH HIGH-SPEED SENSE AMPLIFIER
被引:7
作者
:
FUJII, S
论文数:
0
引用数:
0
h-index:
0
FUJII, S
SAITO, S
论文数:
0
引用数:
0
h-index:
0
SAITO, S
OKADA, Y
论文数:
0
引用数:
0
h-index:
0
OKADA, Y
SATO, M
论文数:
0
引用数:
0
h-index:
0
SATO, M
SAWADA, S
论文数:
0
引用数:
0
h-index:
0
SAWADA, S
SHINOZAKI, S
论文数:
0
引用数:
0
h-index:
0
SHINOZAKI, S
NATORI, K
论文数:
0
引用数:
0
h-index:
0
NATORI, K
OZAWA, O
论文数:
0
引用数:
0
h-index:
0
OZAWA, O
机构
:
来源
:
IEEE JOURNAL OF SOLID-STATE CIRCUITS
|
1986年
/ 21卷
/ 05期
关键词
:
D O I
:
10.1109/JSSC.1986.1052589
中图分类号
:
TM [电工技术];
TN [电子技术、通信技术];
学科分类号
:
0808 ;
0809 ;
摘要
:
引用
收藏
页码:643 / 648
页数:6
相关论文
共 8 条
[1]
A 64K-DRAM WITH 35 NS STATIC COLUMN OPERATION
BABA, F
论文数:
0
引用数:
0
h-index:
0
机构:
FUJITSU LTD,DIV MOS PROC,DEPT SEMICOND ENGN,NAKAHARA KU,KAWASAKI 211,JAPAN
FUJITSU LTD,DIV MOS PROC,DEPT SEMICOND ENGN,NAKAHARA KU,KAWASAKI 211,JAPAN
BABA, F
MOCHIZUKI, H
论文数:
0
引用数:
0
h-index:
0
机构:
FUJITSU LTD,DIV MOS PROC,DEPT SEMICOND ENGN,NAKAHARA KU,KAWASAKI 211,JAPAN
FUJITSU LTD,DIV MOS PROC,DEPT SEMICOND ENGN,NAKAHARA KU,KAWASAKI 211,JAPAN
MOCHIZUKI, H
YABU, T
论文数:
0
引用数:
0
h-index:
0
机构:
FUJITSU LTD,DIV MOS PROC,DEPT SEMICOND ENGN,NAKAHARA KU,KAWASAKI 211,JAPAN
FUJITSU LTD,DIV MOS PROC,DEPT SEMICOND ENGN,NAKAHARA KU,KAWASAKI 211,JAPAN
YABU, T
SHIRAI, K
论文数:
0
引用数:
0
h-index:
0
机构:
FUJITSU LTD,DIV MOS PROC,DEPT SEMICOND ENGN,NAKAHARA KU,KAWASAKI 211,JAPAN
FUJITSU LTD,DIV MOS PROC,DEPT SEMICOND ENGN,NAKAHARA KU,KAWASAKI 211,JAPAN
SHIRAI, K
MIYASAKA, K
论文数:
0
引用数:
0
h-index:
0
机构:
FUJITSU LTD,DIV MOS PROC,DEPT SEMICOND ENGN,NAKAHARA KU,KAWASAKI 211,JAPAN
FUJITSU LTD,DIV MOS PROC,DEPT SEMICOND ENGN,NAKAHARA KU,KAWASAKI 211,JAPAN
MIYASAKA, K
[J].
IEEE JOURNAL OF SOLID-STATE CIRCUITS,
1983,
18
(05)
: 447
-
451
[2]
INOUE Y, 1985, FEB IEEE INT SOL STA, P238
[3]
KIRSCH HC, 1985, FEB ISSCC, P256
[4]
A RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE
KUMANOYA, M
论文数:
0
引用数:
0
h-index:
0
机构:
Mitsubishi Electric Corp, Itami, Jpn, Mitsubishi Electric Corp, Itami, Jpn
KUMANOYA, M
FUJISHIMA, K
论文数:
0
引用数:
0
h-index:
0
机构:
Mitsubishi Electric Corp, Itami, Jpn, Mitsubishi Electric Corp, Itami, Jpn
FUJISHIMA, K
MIYATAKE, H
论文数:
0
引用数:
0
h-index:
0
机构:
Mitsubishi Electric Corp, Itami, Jpn, Mitsubishi Electric Corp, Itami, Jpn
MIYATAKE, H
NISHIMURA, Y
论文数:
0
引用数:
0
h-index:
0
机构:
Mitsubishi Electric Corp, Itami, Jpn, Mitsubishi Electric Corp, Itami, Jpn
NISHIMURA, Y
SAITO, K
论文数:
0
引用数:
0
h-index:
0
机构:
Mitsubishi Electric Corp, Itami, Jpn, Mitsubishi Electric Corp, Itami, Jpn
SAITO, K
MATSUKAWA, T
论文数:
0
引用数:
0
h-index:
0
机构:
Mitsubishi Electric Corp, Itami, Jpn, Mitsubishi Electric Corp, Itami, Jpn
MATSUKAWA, T
YOSHIHARA, T
论文数:
0
引用数:
0
h-index:
0
机构:
Mitsubishi Electric Corp, Itami, Jpn, Mitsubishi Electric Corp, Itami, Jpn
YOSHIHARA, T
NAKANO, T
论文数:
0
引用数:
0
h-index:
0
机构:
Mitsubishi Electric Corp, Itami, Jpn, Mitsubishi Electric Corp, Itami, Jpn
NAKANO, T
[J].
IEEE JOURNAL OF SOLID-STATE CIRCUITS,
1985,
20
(05)
: 909
-
913
[5]
HALF-VDD BIT-LINE SENSING SCHEME IN CMOS DRAMS
LU, NCC
论文数:
0
引用数:
0
h-index:
0
LU, NCC
CHAO, HH
论文数:
0
引用数:
0
h-index:
0
CHAO, HH
[J].
IEEE JOURNAL OF SOLID-STATE CIRCUITS,
1984,
19
(04)
: 451
-
454
[6]
A 1-MBIT CMOS DRAM WITH FAST PAGE MODE AND STATIC COLUMN MODE
SAITO, S
论文数:
0
引用数:
0
h-index:
0
机构:
Toshiba Semiconductor Device, Engineering Lab, Kawasaki, Jpn, Toshiba Semiconductor Device Engineering Lab, Kawasaki, Jpn
SAITO, S
FUJII, S
论文数:
0
引用数:
0
h-index:
0
机构:
Toshiba Semiconductor Device, Engineering Lab, Kawasaki, Jpn, Toshiba Semiconductor Device Engineering Lab, Kawasaki, Jpn
FUJII, S
OKADA, Y
论文数:
0
引用数:
0
h-index:
0
机构:
Toshiba Semiconductor Device, Engineering Lab, Kawasaki, Jpn, Toshiba Semiconductor Device Engineering Lab, Kawasaki, Jpn
OKADA, Y
SAWADA, S
论文数:
0
引用数:
0
h-index:
0
机构:
Toshiba Semiconductor Device, Engineering Lab, Kawasaki, Jpn, Toshiba Semiconductor Device Engineering Lab, Kawasaki, Jpn
SAWADA, S
SHINOZAKI, S
论文数:
0
引用数:
0
h-index:
0
机构:
Toshiba Semiconductor Device, Engineering Lab, Kawasaki, Jpn, Toshiba Semiconductor Device Engineering Lab, Kawasaki, Jpn
SHINOZAKI, S
NATORI, K
论文数:
0
引用数:
0
h-index:
0
机构:
Toshiba Semiconductor Device, Engineering Lab, Kawasaki, Jpn, Toshiba Semiconductor Device Engineering Lab, Kawasaki, Jpn
NATORI, K
OZAWA, O
论文数:
0
引用数:
0
h-index:
0
机构:
Toshiba Semiconductor Device, Engineering Lab, Kawasaki, Jpn, Toshiba Semiconductor Device Engineering Lab, Kawasaki, Jpn
OZAWA, O
[J].
IEEE JOURNAL OF SOLID-STATE CIRCUITS,
1985,
20
(05)
: 903
-
908
[7]
SATO K, 1985, FEB ISSCC, P254
[8]
A 1-MBIT CMOS DYNAMIC RAM WITH A DIVIDED BITLINE MATRIX ARCHITECTURE
TAYLOR, RT
论文数:
0
引用数:
0
h-index:
0
TAYLOR, RT
JOHNSON, MG
论文数:
0
引用数:
0
h-index:
0
JOHNSON, MG
[J].
IEEE JOURNAL OF SOLID-STATE CIRCUITS,
1985,
20
(05)
: 894
-
902
←
1
→
共 8 条
[1]
A 64K-DRAM WITH 35 NS STATIC COLUMN OPERATION
BABA, F
论文数:
0
引用数:
0
h-index:
0
机构:
FUJITSU LTD,DIV MOS PROC,DEPT SEMICOND ENGN,NAKAHARA KU,KAWASAKI 211,JAPAN
FUJITSU LTD,DIV MOS PROC,DEPT SEMICOND ENGN,NAKAHARA KU,KAWASAKI 211,JAPAN
BABA, F
MOCHIZUKI, H
论文数:
0
引用数:
0
h-index:
0
机构:
FUJITSU LTD,DIV MOS PROC,DEPT SEMICOND ENGN,NAKAHARA KU,KAWASAKI 211,JAPAN
FUJITSU LTD,DIV MOS PROC,DEPT SEMICOND ENGN,NAKAHARA KU,KAWASAKI 211,JAPAN
MOCHIZUKI, H
YABU, T
论文数:
0
引用数:
0
h-index:
0
机构:
FUJITSU LTD,DIV MOS PROC,DEPT SEMICOND ENGN,NAKAHARA KU,KAWASAKI 211,JAPAN
FUJITSU LTD,DIV MOS PROC,DEPT SEMICOND ENGN,NAKAHARA KU,KAWASAKI 211,JAPAN
YABU, T
SHIRAI, K
论文数:
0
引用数:
0
h-index:
0
机构:
FUJITSU LTD,DIV MOS PROC,DEPT SEMICOND ENGN,NAKAHARA KU,KAWASAKI 211,JAPAN
FUJITSU LTD,DIV MOS PROC,DEPT SEMICOND ENGN,NAKAHARA KU,KAWASAKI 211,JAPAN
SHIRAI, K
MIYASAKA, K
论文数:
0
引用数:
0
h-index:
0
机构:
FUJITSU LTD,DIV MOS PROC,DEPT SEMICOND ENGN,NAKAHARA KU,KAWASAKI 211,JAPAN
FUJITSU LTD,DIV MOS PROC,DEPT SEMICOND ENGN,NAKAHARA KU,KAWASAKI 211,JAPAN
MIYASAKA, K
[J].
IEEE JOURNAL OF SOLID-STATE CIRCUITS,
1983,
18
(05)
: 447
-
451
[2]
INOUE Y, 1985, FEB IEEE INT SOL STA, P238
[3]
KIRSCH HC, 1985, FEB ISSCC, P256
[4]
A RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE
KUMANOYA, M
论文数:
0
引用数:
0
h-index:
0
机构:
Mitsubishi Electric Corp, Itami, Jpn, Mitsubishi Electric Corp, Itami, Jpn
KUMANOYA, M
FUJISHIMA, K
论文数:
0
引用数:
0
h-index:
0
机构:
Mitsubishi Electric Corp, Itami, Jpn, Mitsubishi Electric Corp, Itami, Jpn
FUJISHIMA, K
MIYATAKE, H
论文数:
0
引用数:
0
h-index:
0
机构:
Mitsubishi Electric Corp, Itami, Jpn, Mitsubishi Electric Corp, Itami, Jpn
MIYATAKE, H
NISHIMURA, Y
论文数:
0
引用数:
0
h-index:
0
机构:
Mitsubishi Electric Corp, Itami, Jpn, Mitsubishi Electric Corp, Itami, Jpn
NISHIMURA, Y
SAITO, K
论文数:
0
引用数:
0
h-index:
0
机构:
Mitsubishi Electric Corp, Itami, Jpn, Mitsubishi Electric Corp, Itami, Jpn
SAITO, K
MATSUKAWA, T
论文数:
0
引用数:
0
h-index:
0
机构:
Mitsubishi Electric Corp, Itami, Jpn, Mitsubishi Electric Corp, Itami, Jpn
MATSUKAWA, T
YOSHIHARA, T
论文数:
0
引用数:
0
h-index:
0
机构:
Mitsubishi Electric Corp, Itami, Jpn, Mitsubishi Electric Corp, Itami, Jpn
YOSHIHARA, T
NAKANO, T
论文数:
0
引用数:
0
h-index:
0
机构:
Mitsubishi Electric Corp, Itami, Jpn, Mitsubishi Electric Corp, Itami, Jpn
NAKANO, T
[J].
IEEE JOURNAL OF SOLID-STATE CIRCUITS,
1985,
20
(05)
: 909
-
913
[5]
HALF-VDD BIT-LINE SENSING SCHEME IN CMOS DRAMS
LU, NCC
论文数:
0
引用数:
0
h-index:
0
LU, NCC
CHAO, HH
论文数:
0
引用数:
0
h-index:
0
CHAO, HH
[J].
IEEE JOURNAL OF SOLID-STATE CIRCUITS,
1984,
19
(04)
: 451
-
454
[6]
A 1-MBIT CMOS DRAM WITH FAST PAGE MODE AND STATIC COLUMN MODE
SAITO, S
论文数:
0
引用数:
0
h-index:
0
机构:
Toshiba Semiconductor Device, Engineering Lab, Kawasaki, Jpn, Toshiba Semiconductor Device Engineering Lab, Kawasaki, Jpn
SAITO, S
FUJII, S
论文数:
0
引用数:
0
h-index:
0
机构:
Toshiba Semiconductor Device, Engineering Lab, Kawasaki, Jpn, Toshiba Semiconductor Device Engineering Lab, Kawasaki, Jpn
FUJII, S
OKADA, Y
论文数:
0
引用数:
0
h-index:
0
机构:
Toshiba Semiconductor Device, Engineering Lab, Kawasaki, Jpn, Toshiba Semiconductor Device Engineering Lab, Kawasaki, Jpn
OKADA, Y
SAWADA, S
论文数:
0
引用数:
0
h-index:
0
机构:
Toshiba Semiconductor Device, Engineering Lab, Kawasaki, Jpn, Toshiba Semiconductor Device Engineering Lab, Kawasaki, Jpn
SAWADA, S
SHINOZAKI, S
论文数:
0
引用数:
0
h-index:
0
机构:
Toshiba Semiconductor Device, Engineering Lab, Kawasaki, Jpn, Toshiba Semiconductor Device Engineering Lab, Kawasaki, Jpn
SHINOZAKI, S
NATORI, K
论文数:
0
引用数:
0
h-index:
0
机构:
Toshiba Semiconductor Device, Engineering Lab, Kawasaki, Jpn, Toshiba Semiconductor Device Engineering Lab, Kawasaki, Jpn
NATORI, K
OZAWA, O
论文数:
0
引用数:
0
h-index:
0
机构:
Toshiba Semiconductor Device, Engineering Lab, Kawasaki, Jpn, Toshiba Semiconductor Device Engineering Lab, Kawasaki, Jpn
OZAWA, O
[J].
IEEE JOURNAL OF SOLID-STATE CIRCUITS,
1985,
20
(05)
: 903
-
908
[7]
SATO K, 1985, FEB ISSCC, P254
[8]
A 1-MBIT CMOS DYNAMIC RAM WITH A DIVIDED BITLINE MATRIX ARCHITECTURE
TAYLOR, RT
论文数:
0
引用数:
0
h-index:
0
TAYLOR, RT
JOHNSON, MG
论文数:
0
引用数:
0
h-index:
0
JOHNSON, MG
[J].
IEEE JOURNAL OF SOLID-STATE CIRCUITS,
1985,
20
(05)
: 894
-
902
←
1
→