ANALYSIS AND DESIGN OF SNUBBER CIRCUITS FOR HIGH-POWER GTO DC-DC CONVERTERS

被引：7

作者：

BRAMBILLA, A ^{[1
]}

DALLAGO, E ^{[1
]}

机构：

[1] UNIV PAVIA,DIPARTIMENTO INGN ELETTR,I-27100 PAVIA,ITALY

来源：

IEEE TRANSACTIONS ON POWER ELECTRONICS | 1994年 / 9卷 / 01期

关键词：

D O I：

10.1109/63.285488

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the analysis and the design of snubber circuits for high power DC-DC converters realized with Gate Turn Off thyristors. These networks are fundamental for the safe operation of semiconductor devices but dissipate some energy. Means to minimize their losses are Studied in this work. The snubber circuits described here are an evolution of the conventional C-snubber and L-snubber. The design of the snubbers is based upon circuits that permit the transfer of the trapped energy to the power source or to the load. Benefits, drawbacks and limits of each new proposed circuit are detailed and studied. Experimental results, obtained from a GTO laboratory prototype converter are reported.

引用

页码：7 / 17

页数：11

共 8 条

[1]

Brambilla A., 1992, IEEE Transactions on Power Electronics, V7, P231, DOI 10.1109/63.124595

[2] A CIRCUIT-LEVEL SIMULATION-MODEL OF PNPN DEVICES [J].