DESIGN OF COMPONENTS FOR A LOW-COST COMBINING SWITCH

被引：7
作者：
DICKEY, SR
KENNER, R
机构：
[1] Courant Institute of Mathematical Sciences, New York University
来源：
VLSI DESIGN | 1995年 / 2卷 / 04期
关键词：
INTERCONNECTION NETWORKS; COMBINING; SHARED MEMORY; FETCH-AND-PHI; SYSTOLIC QUEUES; SWITCH ARCHITECTURE;
D O I：
10.1155/1995/45809
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
We present the design for the two VLSI components used in a processor-to-memory interconnection network for a shared memory system. These components allow the combining of requests that are destined to the same memory location. The design contains both semi-systolic queues and an associative ''wait buffer.'' Transition equations and schematics of the critical pieces of the design are included.
引用
收藏
页码：287 / 303
页数：17
相关论文
共 22 条
[1]  
DICKEY SR, 1992, 21ST P INT C PAR PRO, P110
[2]  
DICKEY SR, 1988, 2ND P S FRONT MASS P, P487
[3]  
DICKEY SR, 1992, 4TH ANN ACM S PAR AL, P296
[4]  
DICKEY SR, 1992, MAR P BROWN MIT C AD, P165
[5]  
DICKEY SS, 1994, THESIS NEW YORK U
[6]  
Edler J., 1985, 12th Annual International Symposium on Computer Architecture Conference Proceedings (Cat. No. 85CH2144-4), P126
[7]   NORA - A RACEFREE DYNAMIC CMOS TECHNIQUE FOR PIPELINED LOGIC STRUCTURES [J].
GONCALVES, NF ;
DEMAN, HJ .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1983, 18 (03) :261-266
[8]  
GOTTLIEB A, 1981, COMPUTER ARCHITE OCT, P16
[9]  
GOTTLIEB A, 1987, EXPT PARALLEL COMPUT, P25
[10]  
GUIBUS LJ, 1982, 1982 P C ADV RES VLS, P155
123